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23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme., , , , , , , , , and 27 other author(s). ISSCC, page 390-391. IEEE, (2017)A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL., , , , , , , , , and 3 other author(s). ISSCC, page 547-556. IEEE, (2006)A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology., , , , , , , , and . IEEE J. Solid State Circuits, 47 (1): 131-140 (2012)A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology., , , , , , , , and . ISSCC, page 502-504. IEEE, (2011)A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 282-283. IEEE, (2008)Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface., , , , , , , , , and 3 other author(s). ISSCC, page 280-281. IEEE, (2008)Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory., , , , , , , , , and 3 other author(s). IRPS, page 40-1. IEEE, (2022)Triangulation of CAD data for visualization using a compact array-based triangle data structure., and . Comput. Graph., 34 (4): 424-429 (2010)Reconstruction of Intima and Adventitia Models into a State Undeformed by a Catheter by Using CT, IVUS, and Biplane X-Ray Angiogram Images., and . Comput. Math. Methods Medicine, (2017)