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Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.

C. Lee, H. Chi, J. Heo, J. Park, J. Jang, D. Lee, J. Jung, D. Lee, D. Kim, K. Kim, S. Kim, D. Park, Y. Lim, G. Park, S. Lee, S. Hong, D. Kwon, I. Hwang, B. Na, K. Kim, S. Choi, H. Choi, Hangi-Jung, W. Bae, J. Ihm, S. Bae, N. Kim, и J. Lee. IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-KoreanischK. Kim. Uni Heidelberg, (2008)

Bongcheol Kim

Kim Gerber

Youngsang Kim

Ryong Kim

Другие публикации лиц с тем же именем

Organizational Virtual Communities: Exploring Motivations Behind Online Panel Participation.T. Daugherty, W. Lee, H. Gangadharbatla, K. Kim, и S. Outhavong. J. Comput. Mediat. Commun., (2005)25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.T. Oh, H. Chung, Y. Cho, J. Ryu, K. Lee, C. Lee, J. Lee, H. Kim, M. Jang, G. Han и 16 other автор(ы). ISSCC, стр. 430-431. IEEE, (2014)A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.D. Kim, B. Song, H. Ahn, W. Ko, S. Do, S. Cho, K. Kim, S. Oh, H. Joo, G. Park и 37 other автор(ы). ISSCC, стр. 448-450. IEEE, (2022)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.J. Heo, K. Kim, D. Lee, C. Lee, D. Moon, K. Kim, J. Baek, S. Yoon, H. Yang, K. Kim и 14 other автор(ы). VLSI Circuits, стр. 114-. IEEE, (2019)A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.H. Ahn, Y. Sung, Y. Kim, J. Kim, K. Kim, D. Lee, Y. Go, J. Lee, J. Jung, Y. Kim и 10 other автор(ы). A-SSCC, стр. 1-4. IEEE, (2023)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.H. Chi, C. Lee, J. Park, J. Heo, J. Jung, D. Lee, D. Kim, D. Park, K. Kim, S. Kim и 29 other автор(ы). ISSCC, стр. 382-384. IEEE, (2020)23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.C. Lee, Y. Eom, J. Park, J. Lee, H. Kim, K. Kim, Y. Choi, H. Chang, J. Kim, J. Bang и 27 other автор(ы). ISSCC, стр. 390-391. IEEE, (2017)An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.C. Lee, H. Chi, J. Heo, J. Park, J. Jang, D. Lee, J. Jung, D. Lee, D. Kim, K. Kim и 18 other автор(ы). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)Distributing Periodic Workload Uniformly Across Time to Achieve Better Service Quality.J. Koh, K. Kim, и H. Shin. IPPS/SPDP Workshops, том 1586 из Lecture Notes in Computer Science, стр. 413-417. Springer, (1999)

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Please choose a person to relate this publication to

Ky ng Kim

Bongcheol Kim

Kim Gerber

Youngsang Kim

Ryong Kim

Другие публикации лиц с тем же именем

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