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Disambiguation of "Lattard, Didier"

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An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications.

, , , , , , , , , and . ESSCIRC, page 426-429. IEEE, (2008)

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Didier Lattard

Alain Lattard

Leo Didier

Didier Béton

Didier Sangiorgio

 

Other publications of authors with the same name

An Integrated Asynchronous Cellular Array to Do Parallel Image Reconstruction., and . MVA, page 128-131. (1988)A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit., , , , , , , , and . ICICDT, page 141-144. IEEE, (2018)Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits., , , , , , , , , and 6 other author(s). IEEE Des. Test, 33 (3): 21-36 (2016)Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects., , , , and . 3DIC, page 1-4. IEEE, (2019)Massively parallel architecture: application to neural net emulation and image reconstruction., , and . ASAP, page 214-225. IEEE, (1990)Advanced 3D Technologies and Architectures for 3D Smart Image Sensors., , , , , , , , , and 7 other author(s). DATE, page 674-679. IEEE, (2019)2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications., , , , , , , , and . CoRR, (2020)A flexible modeling and simulation framework for Design Space Exploration., , and . SoC, page 1-4. IEEE, (2008)Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations., , , , , , and . 3DIC, page 1-5. IEEE, (2019)