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Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology., , , , , and . Microelectron. J., 39 (9): 1130-1139 (2008)A power optimized transconductance amplifier and its application to a 6th order lowpass GmC filter., , , , , , , and . ICECS, page 631-634. IEEE, (2009)A 433-MHz SOI CMOS Automatic Impedance Matching Circuit., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (6): 958-962 (2019)Novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology., , , and . NEWCAS, page 121-124. IEEE, (2017)A frequency measurement BIST implementation targeting gigahertz application., , , , and . ITC, page 1-8. IEEE Computer Society, (2012)Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop., , , and . J. Low Power Electron., 10 (1): 149-162 (2014)Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors., , , , and . J. Electron. Test., 31 (4): 381-394 (2015)VHDL-AMS modeling of a multi-standard phase locked loop., , , , and . ICECS, page 1-4. IEEE, (2005)Built-in test of millimeter-Wave circuits based on non-intrusive sensors., , , , and . DATE, page 505-510. IEEE, (2016)UTBB-FDSOI complementary logic for high quality analog signal processing., , , and . ICECS, page 572-575. IEEE, (2016)