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Crosstalk noise control in an SoC physical design flow.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 488-497 (2004)

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Postroute gate sizing for crosstalk noise reduction., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1670-1677 (2004)Crosstalk noise control in an SoC physical design flow., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (4): 488-497 (2004)Early probabilistic noise estimation for capacitively coupled interconnects., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (3): 337-345 (2003)Incorporating MOS Transistor Mismatches into Training of Analog Neural Networks., , , and . NC, page 669-675. ICSC Academic Press, International Computer Science Conventions, Canada / Switzerland, (1998)Crosstalk Noise in Deep Submicron Integrated Circuit Design. University of Illinois Urbana-Champaign, USA, (2003)Noise propagation and failure criteria for VLSI designs., , , , , , , and . ICCAD, page 587-594. ACM / IEEE Computer Society, (2002)Early probabilistic noise estimation for capacitively coupled interconnects., , , and . SLIP, page 77-83. ACM, (2002)Transistor level gate modeling for accurate and fast timing, noise, and power analysis., , , and . DAC, page 456-461. ACM, (2008)Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model ., , , , and . DATE, page 456-463. IEEE Computer Society, (2002)Static Electromigration Analysis for Signal Interconnects., , , , , and . ISQED, page 377-382. IEEE Computer Society, (2003)