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Test research in Japan.

, , , , , и . IEEE Des. Test, 5 (5): 60-79 (1988)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

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The Complexity of Fault Detection Problems for Combinational Logic Circuits., и . IEEE Trans. Computers, 31 (6): 555-560 (1982)Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , и . VLSI-SoC (Selected Papers), том 249 из IFIP, стр. 301-316. Springer, (2006)An approach to test synthesis from higher level., и . Integr., 26 (1-2): 101-116 (1998)System-on-chip test scheduling with reconfigurable core wrappers., и . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , и . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., и . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , и . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , и . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., и . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)