( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.

, , , и . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Другие публикации лиц с тем же именем

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation., , и . VLSI-SoC (Selected Papers), том 249 из IFIP, стр. 301-316. Springer, (2006)An approach to test synthesis from higher level., и . Integr., 26 (1-2): 101-116 (1998)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)System-on-chip test scheduling with reconfigurable core wrappers., и . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)A cost optimal parallel algorithm for weighted distance transforms., , , и . Parallel Comput., 25 (4): 405-416 (1999)A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings., , , и . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)The Complexity of Fault Detection Problems for Combinational Logic Circuits., и . IEEE Trans. Computers, 31 (6): 555-560 (1982)Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System., , , и . WDAG, том 1320 из Lecture Notes in Computer Science, стр. 290-304. Springer, (1997)Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms., , и . DISC, том 5805 из Lecture Notes in Computer Science, стр. 172-173. Springer, (2009)A Test Generation Method Based on k-Cycle Testing for Finite State Machines., , и . IOLTS, стр. 232-235. IEEE, (2019)