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Register allocation by priority-based coloring (with retrospective)

, и . Best of PLDI, стр. 91-103. ACM, (1984)

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Yu-Kang Chow

Kamal Chowdhury

Ho Ming Chow

Tobias Chowdhury

Kai Uwe Chow

 

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A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor., и . CASES, стр. 9-18. ACM, (2002)Effective Representation of Aliases and Indirect Memory Operations in SSA Form., , , , и . CC, том 1060 из Lecture Notes in Computer Science, стр. 253-267. Springer, (1996)Strength Reduction via SSAPRE., , , , , и . CC, том 1383 из Lecture Notes in Computer Science, стр. 144-158. Springer, (1998)Minimizing Register Usage Penalty at Procedure Calls.. PLDI, стр. 85-94. ACM, (1988)Loop induction variable canonicalization in parallelizing compilers., , и . IEEE PACT, стр. 228-237. IEEE Computer Society, (1996)The Priority-Based Coloring Approach to Register Allocation., и . ACM Trans. Program. Lang. Syst., 12 (4): 501-536 (1990)Partial redundancy elimination in SSA form., , , , , и . ACM Trans. Program. Lang. Syst., 21 (3): 627-676 (1999)Variable Instruction Set Architecture and Its Compiler Support., , , и . IEEE Trans. Computers, 52 (7): 881-895 (2003)A New Algorithm for Partial Redundancy Elimination based on SSA Form., , , , , и . PLDI, стр. 273-286. ACM, (1997)Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution., , , и . MICRO, стр. 148-152. ACM / IEEE Computer Society, (1994)