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A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS., and . IEEE J. Solid State Circuits, 50 (3): 714-723 (2015)Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS., and . IEEE J. Solid State Circuits, 47 (7): 1757-1767 (2012)Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-μm Standard CMOS., , , , , and . IEEE J. Solid State Circuits, 45 (9): 1746-1758 (2010)Self-adaptive lower confidence bound: A new general and effective prescreening method for Gaussian Process surrogate model assisted evolutionary algorithms., , , and . IEEE Congress on Evolutionary Computation, page 1-6. IEEE, (2012)Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (12): 1884-1893 (2010)Behavioral modeling of (coupled) harmonic oscillators., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (8): 1017-1026 (2003)Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (11): 1627-1640 (2009)Guest editorial., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (2): 121-123 (2003)Digital ground bounce reduction by supply current shaping and clock frequency Modulation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 65-76 (2005)Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits., , , , , , and . IEEE J. Solid State Circuits, 37 (11): 1383-1395 (2002)