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Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks., , and . DAC, page 403-408. ACM Press, (1997)Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application., and . ITC, page 245-252. IEEE Computer Society, (2000)Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs., , , , , , , , , and 3 other author(s). ITC, page 1-10. IEEE, (2020)Understanding Power Supply Droop during At-Speed Scan Testing., and . VTS, page 227-232. IEEE Computer Society, (2009)On-chip decoupling capacitor optimization using architectural level prediction., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (3): 319-326 (2002)An architectural solution for the inductive noise problem due to clock-gating., , , and . ISLPED, page 255-257. ACM, (1999)Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure., , , , , and . ITC, page 56-59. IEEE, (2023)Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages., , , and . VTS, page 354-361. IEEE Computer Society, (1996)Efficient diagnosis of path delay faults in digital logic circuits., and . ICCAD, page 471-476. IEEE Computer Society, (1999)Inductive Noise Reduction at the Architectural Level., , , and . VLSI Design, page 162-167. IEEE Computer Society, (2000)