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Другие публикации лиц с тем же именем

Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks., , и . DAC, стр. 403-408. ACM Press, (1997)Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application., и . ITC, стр. 245-252. IEEE Computer Society, (2000)Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs., , , , , , , , , и 3 other автор(ы). ITC, стр. 1-10. IEEE, (2020)Understanding Power Supply Droop during At-Speed Scan Testing., и . VTS, стр. 227-232. IEEE Computer Society, (2009)An architectural solution for the inductive noise problem due to clock-gating., , , и . ISLPED, стр. 255-257. ACM, (1999)On-chip decoupling capacitor optimization using architectural level prediction., , и . IEEE Trans. Very Large Scale Integr. Syst., 10 (3): 319-326 (2002)Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure., , , , , и . ITC, стр. 56-59. IEEE, (2023)Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages., , , и . VTS, стр. 354-361. IEEE Computer Society, (1996)Inductive Noise Reduction at the Architectural Level., , , и . VLSI Design, стр. 162-167. IEEE Computer Society, (2000)Efficient diagnosis of path delay faults in digital logic circuits., и . ICCAD, стр. 471-476. IEEE Computer Society, (1999)