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Disambiguation of "Chatterjee, Abhijit"

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Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks.

, , and . DAC, page 403-408. ACM Press, (1997)

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Abhijit Basu

Abhijit Majumdar

Abhijit Basu

Abhijit Bose

Abhijit Ghose

 

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An adaptive class-E power amplifier with improvement in efficiency, reliability and process variation tolerance., and . ISCAS, page 745-748. IEEE, (2013)Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization., and . IEEE Trans. Computers, 46 (11): 1208-1218 (1997)Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (1): 19-29 (2011)Timing Noise Characterization of High-Speed Digital Bit Sequences Using Incoherent Subsampling and Algorithmic Clock Recovery., , and . IEEE Trans. Instrumentation and Measurement, 63 (12): 2733-2749 (2014)A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing., and . DAC, page 36-39. IEEE Computer Society Press, (1990)Time accelerated Monte Carlo simulations of biological networks using the binomial r-leap method., , , and . Bioinform., 21 (9): 2136-2137 (2005)Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (4): 675-679 (2010)Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums.. IEEE Trans. Very Large Scale Integr. Syst., 1 (2): 138-150 (1993)On the C-Testability of Generalized Counters., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 6 (5): 713-726 (1987)Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2006-2019 (2020)