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Disambiguation of "Donnelly, Kevin S."

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A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC.

, , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 31 (12): 1995-2003 (1996)

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Gerard Donnelly

Alexander Ali Kevin

Francis Dolores Donnelly

Kevin Reddig

Kevin Thurley

 

Other publications of authors with the same name

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 38 (12): 2121-2130 (2003)A 2.6-GByte/s multipurpose chip-to-chip interface., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 33 (11): 1617-1626 (1998)A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM., , , , , and . IEEE J. Solid State Circuits, 29 (12): 1491-1496 (December 1994)A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 31 (12): 1995-2003 (1996)1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus., , , , , , and . IEEE J. Solid State Circuits, 36 (5): 752-760 (2001)A portable digital DLL for high-speed CMOS interface circuits., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 632-644 (1999)A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs., , , , , , , and . IEEE J. Solid State Circuits, 38 (5): 747-754 (2003)