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Diagnosis of MRAM Write Disturbance Fault., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1762-1766 (2010)Write Disturbance Modeling and Testing for MRAM., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (3): 277-288 (2008)Testing methods for quaternary content addressable memory using charge-sharing sensing scheme., , , , , , and . ITC, page 1-10. IEEE, (2015)A Processor-Based Built-In Self-Repair Design for Embedded Memories., , and . Asian Test Symposium, page 366-371. IEEE Computer Society, (2003)An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement., , and . DFT, page 81-92. IEEE Computer Society, (2005)Generalization of an Enhanced ECC Methodology for Low Power PSRAM., , , and . IEEE Trans. Computers, 62 (7): 1318-1331 (2013)Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault., , , and . ATS, page 417-422. IEEE Computer Society, (2008)Fail Pattern Identification for Memory Built-In Self-Repair., , , , , and . Asian Test Symposium, page 366-371. IEEE Computer Society, (2004)Diagnosis for MRAM write disturbance fault., , , , , , and . ITC, page 1-9. IEEE Computer Society, (2007)A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2184-2194 (2011)