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A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

C. Li, T. Tsai, M. Yuan, C. Liao, C. Chang, T. Huang, H. Liao, C. Lu, H. Kuo, K. Hsieh, M. Chen, A. Ximenes, and R. Staszewski. VLSI Circuits, page 1-2. IEEE, (2016)

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Kuo-Hsiang Hung

Kuo-Yi Lim

Yen-Twu Kuo

Ming-fong Kuo

Betram Gordon Kuol

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Benefits of a Closely-Spaced Satellite Constellation of Atmospheric Polarimetric Radio Occultation Measurements.F. Turk, R. Padullés, C. Ao, M. de la Torre Juárez, K. Wang, G. Franklin, S. Lowe, S. Hristova-Veleva, E. Fetzer, E. Cardellach and 2 other author(s). Remote. Sens., 11 (20): 2399 (2019)Self-Supervised Multi-LiDAR Object View Generation Using Single LiDAR.Y. Kuo, C. Shih, H. Lin, and S. Hung. RTCSA, page 18-27. IEEE, (2023)A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS.C. Li, M. Yuan, C. Liao, C. Chang, Y. Lin, T. Tsai, T. Huang, H. Liao, C. Lu, H. Kuo and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (5): 1881-1891 (2021)A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.C. Li, T. Tsai, M. Yuan, C. Liao, C. Chang, T. Huang, H. Liao, C. Lu, H. Kuo, K. Hsieh and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Software-Defined Network Virtualization Platform for Enterprise Network Resource Management.J. Chen, Y. Ma, H. Kuo, C. Yang, and W. Hung. IEEE Trans. Emerg. Top. Comput., 4 (2): 179-186 (2016)CholecSeg8k: A Semantic Segmentation Dataset for Laparoscopic Cholecystectomy Based on Cholec80.W. Hong, C. Kao, Y. Kuo, J. Wang, W. Chang, and C. Shih. CoRR, (2020)Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.M. Chou, Y. Chang, T. Tsai, T. Lu, C. Liao, H. Kuo, R. Sheen, C. Chang, K. Hsieh, A. Loke and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Scalable and Bounded-time Decisions on Edge Device Network using Eclipse Zenoh.C. Shih, H. Lin, Y. Yuan, Y. Kuo, and W. Liang. RTCSA, page 170-179. IEEE, (2022)

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Disambiguation of "Kuo, Hung-Yi"

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DOI
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A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

Please choose a person to relate this publication to

Kuo-Hsiang Hung

Kuo-Yi Lim

Yen-Twu Kuo

Ming-fong Kuo

Betram Gordon Kuol

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kuo, Hung-Yi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.

Please choose a person to relate this publication to

Kuo-Hsiang Hung

Kuo-Yi Lim

Yen-Twu Kuo

Ming-fong Kuo

Betram Gordon Kuol

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.