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Disambiguation of "Rovinski, Austin"

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The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

, , , , , , , , , , and . IEEE Micro, 38 (2): 30--41 (2018)

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Austin Echema

Austin Assoku

Severin Austin

Evan Austin

Howard Austin

 

Other publications of authors with the same name

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (4): 933-944 (2020)Sparse-TPU: adapting systolic arrays for sparse matrices., , , , , , , , , and . ICS, page 19:1-19:12. ACM, (2020)A carbon nanotube transistor based RISC-V processor using pass transistor logic., , , , , and . ISLPED, page 1-6. IEEE, (2017)Bridging Academic Open-Source EDA to Real-World Usability., , , , and . ICCAD, page 111:1-111:7. IEEE, (2020)A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm., , , , , , , , , and 8 other author(s). VLSI Circuits, page 150-. IEEE, (2019)The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips., , , , , , , , , and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge., , , , , , and . ASPLOS, page 615-629. ACM, (2017)A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS., , , , , , , , , and 11 other author(s). VLSI Circuits, page 30-. IEEE, (2019)