%0 Journal Article %1 journals/jssc/BonfantiCGPSS08 %A Bonfanti, Andrea %A Caro, Davide De %A Grasso, Alfio Dario %A Pennisi, Salvatore %A Samori, Carlo %A Strollo, Antonio G. M. %D 2008 %J IEEE J. Solid State Circuits %K dblp %N 6 %P 1403-1413 %T A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#BonfantiCGPSS08 %V 43

@article{journals/jssc/BonfantiCGPSS08, added-at = {2020-08-30T00:00:00.000+0200}, author = {Bonfanti, Andrea and Caro, Davide De and Grasso, Alfio Dario and Pennisi, Salvatore and Samori, Carlo and Strollo, Antonio G. M.}, biburl = {https://www.bibsonomy.org/bibtex/28728a437f809e0069ede5476a6a9b161/dblp}, ee = {https://www.wikidata.org/entity/Q57845762}, interhash = {23b6e32c9e295a78cbe7cb06ddbff233}, intrahash = {8728a437f809e0069ede5476a6a9b161}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 6, pages = {1403-1413}, timestamp = {2020-08-31T11:41:17.000+0200}, title = {A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#BonfantiCGPSS08}, volume = 43, year = 2008 }