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Disambiguation of "Samori, Carlo"

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A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.

, , , , , and . IEEE J. Solid State Circuits, 43 (6): 1403-1413 (2008)

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Paolo Samorí

Lothar Carlowitz

Teresa Carlomagno

Horst Carlowitz

Hans Carlowitz

 

Other publications of authors with the same name

Fast-switching analog PLL with finite-impulse response., , , and . ISCAS (4), page 165-168. IEEE, (2004)Phase noise and accuracy in quadrature oscillators., , , , and . ISCAS (1), page 161-164. IEEE, (2004)A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power., , , , , and . ISSCC, page 88-90. IEEE, (2011)Low-power CMOS IEEE 802.11a/g Signal Separator for Outphasing Transmitter., , , , and . CICC, page 133-136. IEEE, (2006)An efficient method to compute phase-noise in injection-locked frequency dividers., , , and . ISCAS, page 1753-1756. IEEE, (2013)Background adaptive linearization of high-speed digital-to-analog Converters., , , and . ISCAS, page 582-585. IEEE, (2013)A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power., , , and . ISSCC, page 342-344. IEEE, (2012)5-GHz in-phase coupled oscillators with 39% tuning range., , , , and . CICC, page 269-272. IEEE, (2004)Fast simulation techniques for phase noise analysis of oscillators., , , and . ISCAS, page 156-159. IEEE, (2000)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)