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A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.

, , , , , and . IEEE J. Solid State Circuits, 43 (6): 1403-1413 (2008)

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Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs., , and . ISCAS (1), page 525-528. IEEE, (2003)Harmonic distortion in three-stage nested-Miller-compensated amplifiers., and . ISCAS (1), page 485-488. IEEE, (2004)A High-Accuracy High-Speed CMOS Current Comparator., , and . ISCAS, page 739-742. IEEE, (1994)Well-defined design procedure for a three-stage CMOS OTA., , and . ISCAS (3), page 2579-2582. IEEE, (2005)The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (10): 2178-2183 (2007)Sub-Femto-Farad Resolution Electronic Interfaces for Integrated Capacitive Sensors: A Review., , , , and . IEEE Access, (2020)Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads., , and . IET Circuits Devices Syst., 4 (2): 87-98 (2010)Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme., , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (10): 1044-1048 (2006)0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias., , , , , , and . Int. J. Circuit Theory Appl., 48 (1): 15-27 (2020)High-tuning-range CMOS band-pass IF filter based on a low-Q cascaded biquad optimization technique., , , and . Int. J. Circuit Theory Appl., 43 (11): 1615-1636 (2015)