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Disambiguation of "Strollo, Antonio G. M."

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A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.

, , , , , and . IEEE J. Solid State Circuits, 43 (6): 1403-1413 (2008)

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M G Weller

G M Klump

Angelo Strollo

Angelo Strollo

Angelo Strollo

 

Other publications of authors with the same name

A low power control system for real-time tuning of a hybrid transformer-based receiver., , , and . ICECS, page 328-331. IEEE, (2016)NORA based TDC in 90 nm CMOS., , , , , and . Microelectron. J., 44 (6): 489-495 (2013)Analysis of Spread-Spectrum Clocking Modulations Under Synchronization Timing Constraint., , , and . ApplePies, volume 351 of Lecture Notes in Electrical Engineering, page 153-159. Springer, (2014)On the use of approximate adders in carry-save multiplier-accumulators., , , , and . ISCAS, page 1-4. IEEE, (2017)A high performance floating-point special function unit using constrained piecewise quadratic approximation., , and . ISCAS, page 472-475. IEEE, (2008)A VLSI processor for light-weight real-time SAR imaging using signum coded signal and time domain processing., , and . ICECS, page 1631-1634. IEEE, (1999)Approximate Recursive Multipliers Using Low Power Building Blocks., , , , and . ARITH, page 67. IEEE, (2022)A high-speed sense-amplifier based flip-flop., , , and . ECCTD, page 99-102. IEEE, (2005)Shuffled serial adder: an area-latency effective serial adder., , , and . ICECS, page 607-610. IEEE, (2002)A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (7): 1921-1928 (2008)