%0 Journal Article %1 journals/tcad/PossaniRRMR17 %A Possani, Vinicius N. %A Reis, André Inácio %A Ribas, Renato P. %A Marques, Felipe S. %A da Rosa Jr., Leomar S. %D 2017 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 9 %P 1483-1496 %T Transistor Count Optimization in IG FinFET Network Design. %U http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#PossaniRRMR17 %V 36

@article{journals/tcad/PossaniRRMR17, added-at = {2022-03-15T00:00:00.000+0100}, author = {Possani, Vinicius N. and Reis, André Inácio and Ribas, Renato P. and Marques, Felipe S. and da Rosa Jr., Leomar S.}, biburl = {https://www.bibsonomy.org/bibtex/2162aef90f38bfc81dd4a4b21d0bfe3d3/dblp}, ee = {https://doi.org/10.1109/TCAD.2016.2629451}, interhash = {383d8e1457bb4123c5febc712719fa86}, intrahash = {162aef90f38bfc81dd4a4b21d0bfe3d3}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 9, pages = {1483-1496}, timestamp = {2024-04-08T19:47:19.000+0200}, title = {Transistor Count Optimization in IG FinFET Network Design.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad36.html#PossaniRRMR17}, volume = 36, year = 2017 }