( en | de | ru )

 

Disambiguation of "Reis, André Inácio"

Author of the publication

copydeleteadd this publication to your clipboard
Transistor Count Optimization in IG FinFET Network Design.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

André Reis

André Reis

Andre Reis

Inácio Barros

Isabel Inácio

 

Other publications of authors with the same name

A comparative study of CMOS gates with minimum transistor stacks., , , , and . SBCCI, page 93-98. ACM, (2007)Efficient method to compute minimum decision chains of Boolean functions., , , and . ACM Great Lakes Symposium on VLSI, page 419-422. ACM, (2011)Efficient Test Circuit to Qualify Logic Cells., , , and . ISCAS, page 2733-2736. IEEE, (2009)Read-polarity-once Boolean functions., , , and . SBCCI, page 1-6. IEEE, (2013)Tool integration using the web-services approach., , , and . ACM Great Lakes Symposium on VLSI, page 337-340. ACM, (2005)SOP based logic synthesis for memristive IMPLY stateful logic., , , and . ICCD, page 228-235. IEEE Computer Society, (2015)SIFU! - A Didactic Stuck-at Fault Simulator., , and . MSE, page 93-94. IEEE Computer Society, (2003)Fast disjoint transistor networks from BDDs., , , , , and . SBCCI, page 137-142. ACM, (2006)Modeling Subthreshold Leakage Current in General Transistor Networks., , , and . ISVLSI, page 512-513. IEEE Computer Society, (2007)Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering., , , , and . ISQED, page 47-52. IEEE Computer Society, (2008)