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Disambiguation of "Reis, André Inácio"

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Transistor Count Optimization in IG FinFET Network Design.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)

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André Reis

André Reis

Andre Reis

Inácio Barros

Isabel Inácio

 

Other publications of authors with the same name

Comparing Transistor-Level Implementations of 4-Input Logic Functions., , , and . IWLS, page 361-365. (2002)Contributions to Modeling Patent Claims When Representing Patent Knowledge., , , and . AICOL, volume 10791 of Lecture Notes in Computer Science, page 140-156. Springer, (2017)Optimization on cell-library design for digital Application Specific Printed Electronics Circuits., , , , and . PATMOS, page 1-6. IEEE, (2014)Synthesis of threshold logic gates to nanoelectronics., , , and . SBCCI, page 1-6. IEEE, (2013)Design-oriented delay model for CMOS inverter., , and . SBCCI, page 1-6. IEEE, (2012)Binary adder circuit design using emerging MIGFET devices., , , , , and . ISQED, page 125-130. IEEE, (2017)CMOS inverter delay model based on DC transfer curve for slow input., , and . ISQED, page 651-657. IEEE, (2013)Constructive AIG optimization through functional composition., , and . ARCS Workshops, VDE-Verlag, (2011)Transistor-level optimization of CMOS complex gates., , , , , and . LASCAS, page 1-4. IEEE, (2013)Advanced technology mapping for standard-cell generators., and . SBCCI, page 254-259. ACM, (2004)