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Disambiguation of "Marques, Felipe S."

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Transistor Count Optimization in IG FinFET Network Design.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)

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António Marques

Ricardo Marques

Miguel Marques

Nicolas Marques

Euro Marques

 

Other publications of authors with the same name

Post-processing of supergate networks aiming cell layout optimization., , , , , , and . ISCAS, page 1-4. IEEE, (2017)Fast disjoint transistor networks from BDDs., , , , , and . SBCCI, page 137-142. ACM, (2006)Testability Properties of BDDs., , , , and . SBCCI, page 83-88. IEEE Computer Society, (2002)Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability., , , , and . ISCAS, page 1-5. IEEE, (2020)A Novel Sizing Method Aiming Security Against Differential Power Analysis., , , , , and . ICECS, page 429-432. IEEE, (2018)A post-processing methodology to improve the automatic design of CMOS gates at layout-level., , , , , , and . ICECS, page 42-45. IEEE, (2017)Simulated Annealing Applied to LUT-Based FPGA Technology Mapping., , and . MICAI (Special Session), page 23-29. IEEE Computer Society, (2017)NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2012)Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy., , , , , and . SBCCI, page 95-100. IEEE Computer Society, (2002)Transistor-level optimization of CMOS complex gates., , , , , and . LASCAS, page 1-4. IEEE, (2013)