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Disambiguation of "Ribas, Renato P."

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Transistor Count Optimization in IG FinFET Network Design.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)

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Maristella Ribas

Cesar Ribas Cezar

Renato Meola

Renato Hasche

Renato Pasold

 

Other publications of authors with the same name

SwitchCraft: a framework for transistor network design., , , , , and . SBCCI, page 49-53. ACM, (2010)On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design., , , , , and . LATS, page 135-140. IEEE, (2016)KL-Cuts: A new approach for logic synthesis targeting multiple output blocks., , , and . DATE, page 777-782. IEEE Computer Society, (2010)Logic synthesis for manufacturability considering regularity and lithography printability., , , , , and . ISVLSI, page 230-235. IEEE Computer Socity, (2013)Switch level optimization of digital CMOS gate networks., , , and . ISQED, page 324-329. IEEE Computer Society, (2009)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , and . LASCAS, page 227-230. IEEE, (2016)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)ATMR design by construction based on two-level ALS., , , , and . SBCCI, page 1-6. IEEE, (2023)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5126-5130 (2022)Exact lower bound for the number of switches in series to implement a combinational logic cell., , , and . ICCD, page 357-362. IEEE Computer Society, (2005)