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Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias.

, , и . RITA, 19 (1): 28-45 (2012)

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Felicitas Hentschke

Alexander Hentschke

Wolfgang Hentschke

Uwe Hentschke

Christoph Hentschke

 

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A study on the performance of fast initial placement algorithms., , и . VLSI-SOC, стр. 204-. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Cell placement on graphics processing units., , , и . SBCCI, стр. 87-92. ACM, (2007)Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing., , , и . SBCCI, стр. 220-225. ACM, (2006)Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff., , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1073-1086 (2009)Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias., , и . RITA, 19 (1): 28-45 (2012)Improving run times by pruned application of synthesis transforms., , и . SBCCI, стр. 38-43. ACM, (2005)Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations., и . SBCCI, стр. 267-. IEEE Computer Society, (2003)An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias., , , и . VLSI-SoC, стр. 128-133. IEEE, (2006)Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits., , , и . ICECS, стр. 399-402. IEEE, (2006)Blue Macaw: A Didactic Placement Tool Using Simulated Annealing., , и . EDUTECH, том 192 из IFIP, стр. 37-47. Springer, (2005)