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Advancing test compression to the physical dimension., , , , , , , , и . ITC, стр. 1-10. IEEE, (2017)Channel Masking Synthesis for Efficient On-Chip Test Compression., , и . ITC, стр. 452-461. IEEE Computer Society, (2004)Low cost at-speed testing using On-Product Clock Generation compatible with test compression., , , , , , , , и . ITC, стр. 724-733. IEEE Computer Society, (2010)PPA Optimization of Test Points in Automotive Designs., , , , , , , , и . ITC, стр. 204-212. IEEE, (2022)Efficient testing of hierarchical core-based SOCs., , , , , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2014)Low Power Reduced Pin Count Test Methodology., , , , и . ATS, стр. 251-258. IEEE, (2007)Optimizing Test Data Volume Using Hybrid Compression., , , , и . ATS, стр. 157-162. IEEE Computer Society, (2008)Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency., , и . DAC, стр. 158-163. ACM, (2002)Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology., , , , и . ATS, стр. 381-388. IEEE, (2006)Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications., , , , и . ITC, стр. 1-6. IEEE, (2019)