( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation.

, , и . ISSCC, стр. 268-270. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Wei Gu

Wei Gu

Sang-Chun Yeon

Yeon Ha

Wei Wei

 

Другие публикации лиц с тем же именем

Pipelined parallel architecture for high throughput MAP detectors., , и . ISCAS (2), стр. 505-508. IEEE, (2004)A binary-activation, multi-level weight RNN and training algorithm for processing-in-memory inference with eNVM., , и . CoRR, (2019)Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS., , , и . CICC, стр. 1-4. IEEE, (2013)Digital wireline and PLL techniques., и . CICC, IEEE, (2009)A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction., , и . CICC, стр. 459-462. IEEE, (2008)Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators., , , , , , , и . DAC, стр. 1:1-1:6. ACM, (2017)MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles., , , , , , , и . CoRR, (2021)EdgeBERT: Optimizing On-Chip Inference for Multi-Task NLP., , , , , , , , и . CoRR, (2020)Process Variation Tolerant 3T1D-Based Cache Architectures., , , и . MICRO, стр. 15-26. IEEE Computer Society, (2007)Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis., , , , , , , , , и 2 other автор(ы). ASAP, стр. 218-225. IEEE, (2021)