( en | de | ru )

 

Disambiguation of "Levantino, Salvatore"

Author of the publication

copydeleteadd this publication to your clipboard
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter.

, , , , , , , and . ISSCC, page 274-276. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Salvatore Loiero

Fundamentalmetanoia: Untersuchungen zu einem Ort eschato-praktischer Erfahrungs- und Erinnerungskultur. Uni Tübingen, habilitation, (2009)

Salvatore Saputo

Salvatore Cusenza

Salvatore Scarlata

Salvatore Grisanti

 

Other publications of authors with the same name

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band., , , and . ISSCC, page 50-51. IEEE, (2010)Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)Time-to-digital converter with 3-ps resolution and digital linearization algorithm., , , , and . ESSCIRC, page 262-265. IEEE, (2010)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , and . ISSCC, page 188-190. IEEE, (2024)2.9 A Background calibration technique to control bandwidth in digital PLLs., , , and . ISSCC, page 54-55. IEEE, (2014)Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers., , , , , and . ISCAS, page 1-4. IEEE, (2018)A Low-Power and Wide-Locking-Range Injection-Locked Frequency Divider by Three with Dual-Injection Divide-by-Two Technique., , and . ISCAS, page 1-4. IEEE, (2018)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , and . NEWCAS, page 20-24. IEEE, (2022)A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power., , , and . ISSCC, page 342-344. IEEE, (2012)An efficient method to compute phase-noise in injection-locked frequency dividers., , , and . ISCAS, page 1753-1756. IEEE, (2013)