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A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering., , , , , , , , , and 1 other author(s). ISSCC, page 78-79. IEEE, (2023)Digitally-intensive frequency modulators for mm-Wave FMCW radars.. Polytechnic University of Milan, Italy, (2019)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider., , , , and . ISSCC, page 356-357. IEEE, (2013)Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators., , , and . ISCAS, page 1-5. IEEE, (2018)Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper)., , and . CICC, page 1-8. IEEE, (2019)10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion., , , , , , , , and . ISSCC, page 198-200. IEEE, (2024)A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS., , , , , , , and . ISSCC, page 268-270. IEEE, (2019)A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler., , , , , , , , , and 3 other author(s). CICC, page 1-2. IEEE, (2022)A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching., , , , , , , , , and 3 other author(s). ISSCC, page 1-3. IEEE, (2022)