( en | de | ru )

 

Disambiguation of "Khan, Omer"

Author of the publication

copydeleteadd this publication to your clipboard
On the Design of Quantum Graph Convolutional Neural Network in the NISQ-Era and Beyond.

, , , , , , , , and . ICCD, page 290-297. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Emin Sinan Ömeroglu

Lutful Mannan Osama Omer

Osman Hussein Omer

Abrehet Mohammed Omer

Lutful Mannan Osama Omer

 

Other publications of authors with the same name

A model to exploit power-performance efficiency in superscalar processors via structure resizing., and . ACM Great Lakes Symposium on VLSI, page 215-220. ACM, (2010)Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines., and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 293-307. Springer, (2009)POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms., , , and . PACT, page 495-496. IEEE, (2019)A self-adaptive system architecture to address transistor aging., and . DATE, page 81-86. IEEE, (2009)In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores., , , and . IEEE Micro, 40 (1): 83-92 (2020)CoDG-ReRAM: An Algorithm-Hardware Co-design to Accelerate Semi-Structured GNNs on ReRAM., , , , , , , , , and 1 other author(s). ICCD, page 280-289. IEEE, (2022)ConNOC: A Practical Timing Channel Attack on Network-on-chip Hardware in a Multicore Processor., and . HOST, page 192-202. IEEE, (2021)Seeds of SEED: Characterizing Enclave-level Parallelism in Secure Multicore Processors., and . SEED, page 203-209. IEEE, (2021)A framework to accelerate sequential programs on homogeneous multicores., , , and . VLSI-SoC, page 344-347. IEEE, (2013)Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems., , , , , and . RTSS, page 305-316. IEEE Computer Society, (2011)