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A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology., , , , , and . CICC, page 1-4. IEEE, (2015)Analog/Mixed-Signal Layout Optimization using Optimal Well Taps., , , , , , , and . ISPD, page 159-166. ACM, (2022)Formal Verification of Phase-locked Loops Using Reachability Analysis and Continuization, , , , , and . Communications of the ACM, 56 (10): 97--104 (October 2013)Analog Layout Automation On Advanced Process Technologies.. ISPD, page 103. ACM, (2023)Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits., , , , , , and . ICCAD, page 1-9. IEEE, (2021)Efficient statistical analysis of read timing failures in SRAM circuits., , , and . ISQED, page 617-621. IEEE Computer Society, (2009)SRAM parametric failure analysis., , , and . DAC, page 496-501. ACM, (2009)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement., , , , , , and . DATE, page 148-153. IEEE, (2022)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)Indirect phase noise sensing for self-healing voltage controlled oscillators., , , , , , and . CICC, page 1-4. IEEE, (2011)