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Disambiguation of "Yoshimoto, Masahiko"

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Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks.

, , , , , and . ISWCS, page 718-721. IEEE, (2007)

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Masahiko Isaji

Kei Yoshimoto

 

Other publications of authors with the same name

A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668., , , , , , , , , and . IEICE Electron. Express, 15 (12): 20188003 (2018)A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video., , , , , , , , , and . IEICE Electron. Express, 14 (15): 20170668 (2017)Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection., , , , , and . SiPS, page 197-202. IEEE, (2012)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)Quality of a Bit (QoB): A New Concept in Dependable SRAM., , , , , , and . ISQED, page 98-102. IEEE Computer Society, (2008)Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units., , , , , , , and . DSN Workshops, page 91-96. IEEE Computer Society, (2011)A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM., , , , , , , and . ARCS Workshops, page 1-5. VDE Verlag / IEEE Xplore, (2014)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)7T SRAM enabling low-energy simultaneous block copy., , , , , and . CICC, page 1-4. IEEE, (2010)Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system., , , , and . INTERSPEECH, page 1483-1486. ISCA, (2009)