Author of the publication

A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.

, , , , , , , , , and . CICC, page 1-4. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A low power SRAM using auto-backgate-controlled MT-CMOS., , , , , , , and . ISLPED, page 293-298. ACM, (1998)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , and . SoCC, page 143-147. IEEE, (2012)A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure., , , , , and . ISCAS (1), page 73-76. IEEE, (2005)Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 364-372 (2016)A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor., , , , , , , , , and 5 other author(s). ISSCC, page 156-157. IEEE, (2013)The LSI implementation of a memory based field programmable device for MCU peripherals., , , , , , and . DDECS, page 183-188. IEEE Computer Society, (2014)28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 575-584 (2014)FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs., , , , , and . ESSCIRC, page 265-268. IEEE, (2016)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , and . ICCAD, page 398-405. IEEE Computer Society, (2005)A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode., , , and . A-SSCC, page 13-16. IEEE, (2017)