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Disambiguation of "Mori, Haruki"

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A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor.

, , , , , , , , , and . CICC, page 1-4. IEEE, (2015)

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Ryoko Mori

Takahito Mori

Hisako Mori

Magnus Mori

Akira Mori

 

Other publications of authors with the same name

20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices., , , , , , , , , and 14 other author(s). ISSCC, page 360-362. IEEE, (2024)28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning., , , and . ICECS, page 161-164. IEEE, (2018)A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques., , , , , , , , , and 4 other author(s). ISCAS, page 2904-2907. IEEE, (2015)Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros., , , , , , , , , and 1 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1191-1205 (April 2024)A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations., , , , , , , , , and 8 other author(s). ISSCC, page 1-3. IEEE, (2022)A 4nm 6163-TOPS/W/b $4790-TOPS/mm^2/b$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update., , , , , , , , , and 8 other author(s). ISSCC, page 132-133. IEEE, (2023)An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications., , , , , , , , , and 10 other author(s). ISSCC, page 252-254. IEEE, (2021)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications., , , , , , , , and . VLSI Technology and Circuits, page 24-25. IEEE, (2022)Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth., , , , , , , and . ICECS, page 673-676. IEEE, (2018)