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Path delay test compaction with process variation tolerance., , , , , and . DAC, page 845-850. ACM, (2005)DART: Dependable VLSI test architecture and its implementation., , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout., , , , and . ITC, page 83-89. IEEE Computer Society, (2002)On validating data hold times for flip-flops in sequential circuits., , , , , and . ITC, page 317-325. IEEE Computer Society, (2000)On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits., , and . Asian Test Symposium, page 147-152. IEEE Computer Society, (1999)An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification., , and . Asian Test Symposium, page 58-63. IEEE Computer Society, (1998)On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression., , , , , and . VLSI Design, page 279-284. IEEE Computer Society, (2013)Hybrid BIST Using Partially Rotational Scan., , , , and . Asian Test Symposium, page 379-384. IEEE Computer Society, (2001)On Improving Defect Coverage of Stuck-at Fault Tests., , , , and . Asian Test Symposium, page 216-223. IEEE Computer Society, (2005)On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume., , , and . ICCD, page 387-396. IEEE Computer Society, (2003)