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Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design., , , , и . Parallel Process. Lett., 27 (3-4): 1750006:1-1750006:17 (2017)REDEFINE®™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress)., , , , , и . CASES, стр. 15:1-15:2. ACM, (2017)Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array., , , , и . iNIS, стр. 7-12. IEEE, (2015)A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks., , , , , , , , и . VLSID, стр. 505-510. IEEE Computer Society, (2015)Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs., , , , , , , и . ICSAMOS, стр. 225-232. IEEE, (2014)Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures., , , , и . ARC, том 5453 из Lecture Notes in Computer Science, стр. 204-215. Springer, (2009)Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders., , , и . ASAP, стр. 287-292. IEEE Computer Society, (2008)A Framework for QoS Adaptive Grid Meta Scheduling., , , , и . DEXA Workshops, стр. 292-296. IEEE Computer Society, (2005)Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture., , , , , и . ARC, том 6578 из Lecture Notes in Computer Science, стр. 125-132. Springer, (2011)Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations., , , , , , , , , и 1 other автор(ы). VLSID, стр. 153-158. IEEE Computer Society, (2015)