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Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.

, , , , , , , , , , , и . DFT, стр. 358-366. IEEE Computer Society, (2010)

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Jiryo Furukawa

Hiroshi Kawabe

Hiroshi Murata

Hiroshi Kubota

Hiroshi Uchida

 

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