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Disambiguation of "Jone, Wen-Ben"

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Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.

, , , , , , , , , , , and . DFT, page 358-366. IEEE Computer Society, (2010)

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Hugh Jones

Josef Edgar Jonek

Martina Jonen

Lars Jonetz-Mentzel

Stefan Joneleit

 

Other publications of authors with the same name

On random testing for combinational circuits with a high measure of confidence., and . IEEE Trans. Syst. Man Cybern., 22 (4): 748-754 (1992)Fault Modeling and Detection for Drowsy SRAM Caches., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (6): 1084-1100 (2007)A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (3): 374-384 (1995)DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip., , and . DAC, page 849-852. ACM, (2006)Fault Modeling and Detection for Drowsy SRAM Caches., , and . ITC, page 1-10. IEEE Computer Society, (2006)An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers., , and . VLSI Design, page 379-384. IEEE Computer Society, (2001)Charge sharing fault analysis and testing for CMOS domino logic circuits., , , and . Asian Test Symposium, page 435-440. IEEE Computer Society, (2000)An Efficient BIST Method for Small Buffers., , , and . VTS, page 246-251. IEEE Computer Society, (1999)Post-placement voltage island generation for timing-speculative circuits., , , , and . DAC, page 112:1-112:6. ACM, (2013)Material Fatigue and Reliability of MEMS Accelerometers., , and . DFT, page 314-322. IEEE Computer Society, (2008)