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Disambiguation of "Touba, Nur A."

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Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.

, , , , , , , , , , , and . DFT, page 358-366. IEEE Computer Society, (2010)

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Farid Toubal

Nicolas Toubanakis

Frank Eugen Toubartz

Nur Amin

Nur en Kurt

 

Other publications of authors with the same name

Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories., , and . VLSI-SoC, page 195-200. IEEE, (2012)Selective Checksum based On-line Error Correction for RRAM based Matrix Operations., and . VTS, page 1-6. IEEE, (2020)A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation., and . VTS, page 1-6. IEEE, (2019)An efficient test vector compression scheme using selective Huffman coding., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 797-806 (2003)Test data compression using dictionaries with selective entries and fixed-length indices., , and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 470-490 (2003)Low-power weighted pseudo-random BIST using special scan cells., , , and . ACM Great Lakes Symposium on VLSI, page 86-91. ACM, (2004)X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR.. ITC, page 1-10. IEEE Computer Society, (2007)Synthesis of nonintrusive concurrent error detection using an even error detecting function., and . ITC, page 8. IEEE Computer Society, (2005)Improving test compression with scan feedforward techniques., and . ITC, page 1-10. IEEE Computer Society, (2014)An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets., , and . Asian Test Symposium, page 275-. IEEE Computer Society, (1999)