Author of the publication

Improving DRAM performance by parallelizing refreshes with accesses.

, , , , , , and . HPCA, page 356-367. IEEE Computer Society, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism., , , , , , , , and . CoRR, (2016)Improving DRAM performance by parallelizing refreshes with accesses., , , , , , and . HPCA, page 356-367. IEEE Computer Society, (2014)MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect., , , , , and . NOCS, page 1-10. IEEE Computer Society, (2012)Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems., , , , and . ISCA, page 416-427. IEEE Computer Society, (2012)HAT: Heterogeneous Adaptive Throttling for On-Chip Networks., , , and . SBAC-PAD, page 9-18. IEEE Computer Society, (2012)DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators., , , and . ACM Trans. Archit. Code Optim., 12 (4): 65:1-65:28 (2016)Adaptive-latency DRAM: Optimizing DRAM timing for the common-case., , , , , , and . HPCA, page 489-501. IEEE Computer Society, (2015)Design and Evaluation of Hierarchical Rings with Deflection Routing., , , , , , , and . SBAC-PAD, page 230-237. IEEE Computer Society, (2014)