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Disambiguation of "Hamzaoglu, Fatih"

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SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.

, , , , , , , , and . IEEE J. Solid State Circuits, 40 (4): 895-901 (2005)

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Abdelhak Fatihi

Fatih Bayazit

Fatih Bilgili

Fatih Ceteci

Fatih Koyuncu

 

Other publications of authors with the same name

Circuit-level techniques to control gate leakage for sub-100nm CMOS., and . ISLPED, page 60-63. ACM, (2002)A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply., , , , , , , , and . IEEE J. Solid State Circuits, 41 (1): 146-151 (2006)Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process., , , , , , and . IEEE J. Solid State Circuits, 45 (4): 751-758 (2010)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 2572-2581. IEEE, (2006)An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS., , , and . CICC, page 1-4. IEEE, (2017)Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs., , , , and . VLSI Technology and Circuits, page 112-113. IEEE, (2022)16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing., , , , , and . ISSCC, page 248-250. IEEE, (2021)A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation., , , , , , , and . ISSCC, page 346-347. IEEE, (2010)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology., , , , , , , , , and . ISSCC, page 376-377. IEEE, (2008)