( en | de | ru )

 

Disambiguation of "Bhattacharya, Uddalak"

Author of the publication

copydeleteadd this publication to your clipboard
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.

, , , , , , , , and . IEEE J. Solid State Circuits, 41 (1): 146-151 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Subhamoy Bhattacharya

Chhaya Bhattacharya

Nupur Bhattacharya

Indrajit Bhattacharya

Asitesh Bhattacharya

 

Other publications of authors with the same name

A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist., , , , , and . VLSIC, page 266-. IEEE, (2015)A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 148-154 (2009)Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology., , , and . Integr., (2020)SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction., , , , , , , , and . IEEE J. Solid State Circuits, 40 (4): 895-901 (2005)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry., , , , , , , , and . ISSCC, page 230-232. IEEE, (2012)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process., , , , , and . VLSIC, page 174-. IEEE, (2015)17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply., , , , , , , , and . IEEE J. Solid State Circuits, 41 (1): 146-151 (2006)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)