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Reconfigurable asynchronous pipelines: From formal models to silicon.

, , and . DATE, page 1562-1567. IEEE, (2018)

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Registers for Phase Difference Based Logic., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (6): 720-724 (2007)An Excitation Time Model for General-purpose Memristance Tuning Circuit., , , and . ISCAS, page 1-5. IEEE, (2018)Significance-Driven Logic Compression for Energy-Efficient Multiplier Design., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (3): 417-430 (2018)Step Persistence in the Design of GALS Systems., , , , and . Petri Nets, volume 7927 of Lecture Notes in Computer Science, page 190-209. Springer, (2013)Toward Designing Thermally-Aware Memristance Decoder., , , , and . ISCAS, page 1. IEEE, (2020)Online Testing by Protocol Decomposition., , , and . IOLTS, page 263-268. IEEE Computer Society, (2006)Reconfigurable asynchronous pipelines: From formal models to silicon., , and . DATE, page 1562-1567. IEEE, (2018)Power proportional adder design for Internet of Things in a 65 nm process., , , and . PATMOS, page 1-6. IEEE, (2017)Empirical Temperature Model of Self-Directed Channel Memristor., , , , , and . IEEE SENSORS, page 1-4. IEEE, (2020)STG Optimisation in the Direct Mapping of Asynchronous Circuits ., , and . DATE, page 10932-10939. IEEE Computer Society, (2003)