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Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory.

, , , и . ICECS, стр. 123-124. IEEE, (2019)

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Johannes Marcour

Hans-Ernst Marcolin

Monika Marcotty

Carlos Javier Marcos Navas

Massimiliano Marcon

 

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Low bit rate image compression core for onboard space applications., , , , и . IEEE Trans. Circuits Syst. Video Techn., 16 (1): 114-128 (2006)Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications., , и . ISLPED, стр. 161-166. ACM, (2005)Design of a sub-1-V nanopower CMOS current reference., , , и . ECCTD, стр. 1-4. IEEE, (2017)Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory., , , и . ICECS, стр. 123-124. IEEE, (2019)An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops., , , и . ICECS, стр. 158-161. IEEE, (2019)A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm2 Area in 180nm., , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2020)Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework., , , , , , и . Integr., (2020)A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion., , , , и . CoRR, (2022)Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider., , , и . ICECS 2022, стр. 1-4. IEEE, (2022)STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications., , , и . LASCAS, стр. 1-4. IEEE, (2023)