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Multi-cell soft errors at the 16-nm FinFET technology node., , , , , , and . IRPS, page 4. IEEE, (2015)Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node., , , , , and . IRPS, page 46. IEEE, (2024)Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node., , , , and . IRPS, page 1-6. IEEE, (2023)Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment., , , , , , , , , and 1 other author(s). IRPS, page 7. IEEE, (2022)Soft Error Rate Predictions for Terrestrial Neutrons at the 3-nm Bulk FinFET Technology., , , , and . IRPS, page 1-6. IEEE, (2023)High-Current State triggered by Operating-Frequency Change., , , , , , and . IRPS, page 1-4. IEEE, (2020)Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages., , , , and . IRPS, page 1-5. IEEE, (2024)Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET., , , , , , , and . IRPS, page 10. IEEE, (2024)Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET., , , , , and . IRPS, page 1-5. IEEE, (2021)Single-Event Latchup Vulnerability at the 7-nm FinFET Node., , , , and . IRPS, page 5. IEEE, (2022)