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Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node.

Y. Xiong, N. Pieper, J. Kronenberg, D. Ball, M. Casey, and B. Bhuva. IRPS, page 46. IEEE, (2024)

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Suthinee Bhuvanath

Thangaraj Selvaraj Bhuvaneish

Bharat Balasubramanian

Bharat Kurana

Bharat Kalra

Other publications of authors with the same name

Terrestrial SER characterization for nanoscale technologies: A comparative study.N. Mahatme, B. Bhuva, N. Gaspard, T. Assis, Y. Xu, P. Marcoux, M. Vilchis, B. Narasimham, A. Shih, S. Wen and 5 other author(s). IRPS, page 4. IEEE, (2015)High-Current State triggered by Operating-Frequency Change.L. Xu, J. Cao, S. Wen, R. Fung, J. Markevitch, D. Ball, and B. Bhuva. IRPS, page 1-4. IEEE, (2020)Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology.L. Xu, J. Cao, B. Bhuva, I. Chatterjee, S. Wen, R. Wong, and L. Massengill. IRPS, page 1-5. IEEE, (2019)Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages.J. Kronenberg, Y. Xiong, N. Pieper, D. Ball, and B. Bhuva. IRPS, page 1-5. IEEE, (2024)Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs.B. Narasimham, J. Wang, N. Vedula, S. Gupta, B. Bartz, C. Monzel, I. Chatterjee, B. Bhuva, R. Schrimpf, and R. Reed. IRPS, page 2. IEEE, (2015)Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node.Y. Xiong, A. Feeley, L. Massengill, B. Bhuva, S. Wen, and R. Fung. IRPS, page 1-5. IEEE, (2021)Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology.A. Feeley, Y. Xiong, B. Bhuva, B. Narasimham, S. Wen, and R. Fung. IRPS, page 1-5. IEEE, (2021)Single-event effects on optical transceiver.K. Lezon, S. Wen, Y. Dan, R. Wong, and B. Bhuva. IRPS, page 6-1. IEEE, (2018)Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology.H. Zhang, H. Jiang, M. Eaker, K. Lezon, B. Narasimham, N. Mahatme, L. Massengill, and B. Bhuva. IRPS, page 1. IEEE, (2018)Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET.B. Narasimham, A. Montoya, C. Paone, T. Riehle, M. Smith, L. Tsau, D. Ball, and B. Bhuva. IRPS, page 10. IEEE, (2024)

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Disambiguation of "Bhuva, Bharat L."

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Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node.

Please choose a person to relate this publication to

Suthinee Bhuvanath

Thangaraj Selvaraj Bhuvaneish

Bharat Balasubramanian

Bharat Kurana

Bharat Kalra

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bhuva, Bharat L."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node.

Please choose a person to relate this publication to

Suthinee Bhuvanath

Thangaraj Selvaraj Bhuvaneish

Bharat Balasubramanian

Bharat Kurana

Bharat Kalra

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node.