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FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)., , , , , , , , , and 5 other author(s). IEEE Des. Test, 41 (1): 70-80 (February 2024)Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor., , , , , , , , , and 33 other author(s). ISCAS, page 443-447. IEEE, (2022)Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project., , , , , , , , , and 11 other author(s). DAC, page 76. ACM, (2019)A carbon nanotube transistor based RISC-V processor using pass transistor logic., , , , , and . ISLPED, page 1-6. IEEE, (2017)Bridging Academic Open-Source EDA to Real-World Usability., , , , and . ICCAD, page 111:1-111:7. IEEE, (2020)Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm., , , , , , , , , and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding., , , , , , , and . ISLPED, page 23:1-23:6. ACM, (2022)An Open-source Framework for Autonomous SoC Design with Analog Block Generation., , , , , , , , , and 3 other author(s). VLSI-SOC, page 141-146. IEEE, (2020)Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation., , , , , , , , , and 5 other author(s). VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 65-85. Springer, (2020)Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 986-998 (2022)