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Disambiguation of "Zhao, Weisheng"

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A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication.

, , , , , , and . NANOARCH, page 1-6. IEEE, (2021)

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Zhao Zhao

Yanning Zhao

Hertz-level ultra-stable laser and its application to high precision spectroscopy. Uni Erlangen-Nürnberg, (2009)

Xiaojian Zhao

Ruoyao Zhao

Bingbing Zhao

 

Other publications of authors with the same name

Nanocomputing Block based Multi-Context FPGA., , and . ERSA, page 297-298. CSREA Press, (2009)Magnetic memory (MRAM), a new area for 2D and 3D SoC/SiP design., and . ACM Great Lakes Symposium on VLSI, page 429-430. ACM, (2011)Low power magnetic flip-flop based on checkpointing and self-enable mechanism., , , , and . NEWCAS, page 1-4. IEEE, (2013)Emerging hybrid logic circuits based on non-volatile magnetic memories., , , , , and . NEWCAS, page 1-4. IEEE, (2013)Deep Neural Network accelerator with Spintronic Memory., , , and . ACM Great Lakes Symposium on VLSI, page 51. ACM, (2020)A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output., , , , , , , , and . ICTA, page 123-124. IEEE, (2021)Implementation of 16 Boolean logic operations based on one basic cell of spin-transfer-torque magnetic random access memory., , , , , , , , , and 4 other author(s). Sci. China Inf. Sci., (June 2023)Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (7): 2151-2162 (July 2024)CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (7): 2084-2097 (July 2024)Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers., , , , , , and . DATE, page 119-124. IEEE, (2018)