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Execution modeling in self-aware FPGA-based architectures for efficient resource management.

A. Rodríguez, J. Valverde, C. Castanares, J. Portilla, E. de la Torre, and T. Riesgo. ReCoSoC, page 1-8. IEEE, (2015)

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Juan Fernández Valverde

Isabel Valverde

Hsiao-Mei Juan

Alexander Juan

Elias Valverde

Other publications of authors with the same name

Design of OpenCL-Compatible Multithreaded Hardware Accelerators with Dynamic Support for Embedded FPGAsA. "Rodriguez, J. "Valverde, and E. "de la Torre. (2015)Power management techniques in an FPGA-based WSN node for high performance applications.M. Lombardo, J. Camarero, J. Valverde, J. Portilla, E. de la Torre, and T. Riesgo. ReCoSoC, page 1-8. IEEE, (2012)Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs.A. Rodríguez, J. Valverde, and E. de la Torre. ReConFig, page 1-7. IEEE, (2015)A Fast Prototyping Workflow for Reconfigurable SDR Applications.A. Gener, J. Valverde, J. Otero, and P. Harris. ReCoSoC, page 66-73. IEEE, (2019)Optimal energy collection with rotational movement constraints in concentrated solar power plants.J. Díaz-Báñez, J. Higes-López, M. Pérez-Cutiño, and J. Valverde. Eur. J. Oper. Res., 317 (2): 631-642 (2024)Power-aware multi-objective evolvable hardware system on an FPGA.B. López, J. Valverde, E. de la Torre, and T. Riesgo. AHS, page 61-68. IEEE, (2014)Execution modeling in self-aware FPGA-based architectures for efficient resource management.A. Rodríguez, J. Valverde, C. Castanares, J. Portilla, E. de la Torre, and T. Riesgo. ReCoSoC, page 1-8. IEEE, (2015)FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework.A. Rodríguez, J. Valverde, J. Portilla, A. Otero, T. Riesgo, and E. de la Torre. Sensors, 18 (6): 1877 (2018)Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration.A. Rodríguez, J. Valverde, E. de la Torre, and T. Riesgo. ReCoSoC, page 1-7. IEEE, (2014)Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform.A. Rodríguez, J. Valverde, C. Castanares, J. Portilla, E. de la Torre, and T. Riesgo. ISCAS, page 1902. IEEE, (2015)

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Disambiguation of "Valverde, Juan"

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Execution modeling in self-aware FPGA-based architectures for efficient resource management.

Please choose a person to relate this publication to

Juan Fernández Valverde

Isabel Valverde

Hsiao-Mei Juan

Alexander Juan

Elias Valverde

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Valverde, Juan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Execution modeling in self-aware FPGA-based architectures for efficient resource management.

Please choose a person to relate this publication to

Juan Fernández Valverde

Isabel Valverde

Hsiao-Mei Juan

Alexander Juan

Elias Valverde

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Execution modeling in self-aware FPGA-based architectures for efficient resource management.