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Execution modeling in self-aware FPGA-based architectures for efficient resource management.

, , , , , и . ReCoSoC, стр. 1-8. IEEE, (2015)

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Martino La Torre

Hector la Torre

Luis La Torre

Silvia Eunice Gutiérrez de la Torre Julius-Maximilians-Universität Würzburg

Eduardo La Riega

 

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A digital system to emulate wireless networks., , , и . IET Comput. Digit. Tech., 1 (5): 444-450 (2007)Automatic generation of identical routing pairs for FPGA implemented DPL logic., , , и . ReConFig, стр. 1-6. IEEE, (2012)Generic Systolic Array for Run-Time Scalable Cores., , , и . ARC, том 5992 из Lecture Notes in Computer Science, стр. 4-16. Springer, (2010)Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support., , , , , и . AHS, стр. 184-191. IEEE, (2011)Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems., , , , , и . ReConFig, стр. 164-169. IEEE Computer Society, (2011)Power-aware multi-objective evolvable hardware system on an FPGA., , , и . AHS, стр. 61-68. IEEE, (2014)A Modular Peripheral to Support Self-Reconfiguration in SoCs., , , , и . DSD, стр. 88-95. IEEE Computer Society, (2010)A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC., , , , , и . CPS Summer School, PhD Workshop, том 2457 из CEUR Workshop Proceedings, стр. 107-118. CEUR-WS.org, (2019)Message from the chairs., , , и . ReCoSoC, стр. 1. IEEE, (2015)A dynamic communication strategy for the distributed ATPG system DPLATON., , , и . EURO-DAC, стр. 271-276. IEEE Computer Society, (1993)